Position: Senior Design Engineer
Job Code: DV1081

Responsibilities:

• Design & verification of a high performance PHY SOC
• Contribute to the development of overall design, debug strategy, simulation environment, coverage methodology
• Contribute to creation of IC test plans and hands-on development of test bench
• Test case development via VERILOG
• Design/develop models for test environment setup
• Run simulations, debug and document failures
• Create and analyze coverage metrics to ensure completeness
• Analyze test failures and aid in debugging logic designs

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Qualifications:

• MSEE with 5 plus years experience in IC design and verification
• Working experience with designs requiring compliance to standard specifications
• Familiar with Verilog, verification environment, common RTL simulation and verification tools
• System-level and block-level verification
• Good understanding of IC design fundamentals, synthesis, JTAG, DFT, etc.

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Desirable:

• Experience with system Verilog, formal checking tools and assertions
• Experience with programming languages: C/C++, PERL, PLI
• Familiarity with DSP and PHY layer communication protocols for 802.3

Apply now at careers@platonetworks.com