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Position: Senior Staff Backend Design Engineer
Job Code: DB1084 Responsibilities: Primary responsibility will be for participating in the design and development of advanced process technologies networking applications. This will include engineering design flow, scripting, synthesis, floor-plan, place and route, timing closure, LBIST, MEMBIST, JTAG, DFT, ATPG, library characterization and maintaining, memory compilation, DRC/LVS, etc. Responsibilities will also include working with front-end engineers to optimize the design for place and route The role might also involve managing key design service vendors to provide technical support and follow up milestones of schedule. Qualifications: MSEE preferred with 12+ years experience High speed (>500MHz) ASIC backend design and Place and Route experience Intensive logic synthesis and timing closure experience using Cadence/Synopsys tools Experience with DFT, ATPG, MEMBIST, etc. Experience with CAD design, standard cell libraries, mixed-signal interface, etc Experience with transporting of mixed signal schematic/layout flow and digital place and route flow Experience in networking IC design in RTL Good communication and people skills Experience in interfacing with external organizations will be a plus Experience with Ethernet PHY products will be a plus Experience with XAUI and/or high speed analog systems a plus Knowledge in analog/digital VLSI design will be a plus Apply now at careers@platonetworks.com |
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Copyright © 2006 Plato Networks, Inc. |
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